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P4C163-35PM Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C163-35PM Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 12 page P4C163/163L Page 6 of 12 Document # SRAM120 REV C -25 -35 -45 Min Max Min Max Min Max t WC Write Cycle Time 25 35 45 ns t CW Chip Enable 18 25 33 ns Time to End of Write t AW Address Valid to 18 25 33 ns End of Write t AS Address Set-up Time 0 0 0 ns t WP Write Pulse Width 18 20 25 ns t AH Address Hold Time 0 0 0 ns t DW Data Valid to End 13 15 20 ns of Write t DH Data Hold Time 0 0 0 ns t WZ Write Enable to 10 14 18 ns Output in High Z t OW Output Active 3 5 5 ns from End of Write AC CHARACTERISTICS—WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Symbol Parameter Unit WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(11) Notes: 11. CE 1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show t WZ and tOW. 13. If CE 1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a low impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. |
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