CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C
Page 3 of 49
event, and subtracting the two values. The four capture timers
save a programmable 8 bit range of the free-running timer
when a GPIO edge occurs on the two capture pins (P0.0,
P0.1).
The CY7C637xxC includes an integrated USB serial interface
engine (SIE) that supports the integrated peripherals. The
hardware supports one USB device address with three
endpoints. The SIE allows the USB host to communicate with
the function integrated into the microcontroller. A 3.3V
regulated output pin provides a pull-up source for the external
USB resistor on the D– pin.
The USB D+ and D– USB pins can alternately be used as PS/2
SCLK and SDATA signals, so that products can be designed
to respond to either USB or PS/2 modes of operation. PS/2
operation is supported with internal pull-up resistors on SCLK
and SDATA, the ability to disable the regulator output pin, and
an interrupt to signal the start of PS/2 activity. No external
components are necessary for dual USB and PS/2 systems,
and no GPIO pins need to be dedicated to switching between
modes. Slow edge rates operate in both modes to reduce EMI.
4.0
Pin Configurations
1
2
3
4
5
6
9
11
15
16
17
18
19
20
22
21
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
VSS
VREG/P2.0
P0.6
P1.5
P1.1
P1.3
D+/SCLK
P1.7
D–/SDATA
VCC
14
P0.7
10
VPP
XTALIN/P2.1
XTALOUT
12
13
7
8
P1.4
P1.6
24
23
P0.4
P0.5
24-pin SOIC/PDIP/QSOP
CY7C63743C
1
2
3
4
6
7
8
10
11
12
13
15
16
18
17
P0.0
P0.1
P0.2
P0.3
VSS
VREG/P2.0
P0.4
P0.6
P0.7
D+/SCLK
D–/SDATA
VCC
18-pin SOIC/PDIP
P0.5
9
VPP
XTALIN/P2.1
XTALOUT
CY7C63723C
5
14
P1.0
P1.1
Top View
4
5
6
7
8
9
22
21
20
19
18
17
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VSS
D+/SCLK
P0.7
P1.1
P1.3
P1.5
P1.7
CY7C63722C-XC
DIE
10
5.0
Pin Definitions
Name
I/O
CY7C63723C CY7C63743C CY7C63722C
Description
18-Pin
24-Pin
25-Pad
D–/SDATA,
D+/SCLK
I/O
12
13
15
16
16
17
USB differential data lines (D– and D+), or PS/2 clock
and data signals (SDATA and SCLK)
P0[7:0]
I/O
1, 2, 3, 4,
15, 16, 17, 18
1, 2, 3, 4,
21, 22, 23, 24
1, 2, 3, 4,
22, 23, 24, 25
GPIO Port 0 capable of sinking up to 50 mA/pin, or
sinking controlled low or high programmable current.
Can also source 2 mA current, provide a resistive
pull-up, or serve as a high-impedance input. P0.0 and
P0.1 provide inputs to Capture Timers A and B, respec-
tively.
P1[7:0]
I/O
5, 14
5, 6, 7, 8,
17, 18, 19, 20
5, 6, 7, 8,
18, 19, 20, 21
IO Port 1 capable of sinking up to 50 mA/pin, or sinking
controlled low or high programmable current. Can also
source 2 mA current, provide a resistive pull-up, or
serve as a high-impedance input.
XTALIN/P2.1
IN
9
12
13
6-MHz ceramic resonator or external clock input, or
P2.1 input
XTALOUT
OUT
10
13
14
6-MHz ceramic resonator return pin or internal oscillator
output
VPP
7
10
11
Programming voltage supply, ground for normal
operation
VCC
11
14
15
Voltage supply
VREG/P2.0
8
11
12
Voltage supply for 1.3-k
Ω USB pull-up resistor (3.3V
nominal). Also serves as P2.0 input.
VSS
6
9
9, 10
Ground
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