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CS98ULPA877AHLF-T Datasheet(PDF) 7 Page - Integrated Device Technology

Part # CS98ULPA877AHLF-T
Description  1.8V Low-Power Wide-Range Frequency Clock Driver
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

CS98ULPA877AHLF-T Datasheet(HTML) 7 Page - Integrated Device Technology

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ICS98ULPA877A
Advance Information
1177C—05/23/07
Notes:
1.
Switching characteristics guaranteed for application frequency range.
2.
Static phase offset shifted by design.
Switching Characteristics
1
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
(MHz)
MIN
TYP
MAX
UNITS
Output enable time
ten
OE to any output
4.73
8
ns
Output disable time
tdis
OE to any output
5.82
8
ns
160 to 270
-40
40
ps
271 to 410
-30
30
ps
160 to 270
-60
60
ps
271 to 410
-50
50
ps
Input Clock
1
2.5
4
v/ns
Output Enable (OE), (OS)
0.5
v/ns
Output clock slew rate
SLr1(o)
1.5
2.5
3
v/ns
tjit(cc+)
040
ps
tjit(cc-)
0
-40
ps
160 to 270
-50
50
ps
271 to 410
-20
20
ps
Static Phase Offset
tSPO
2
271 to 410
-50
0
50
ps
t jit (per) + t (Ø)dyn + t skew(o)
(su)
80
ps
t(Ø)dyn + tskew(o)
t (h)
60
ps
160 to 270
40
ps
271 to 410
30
ps
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency
deviation
0.00
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
160 to 410
Period jitter
tjit (per)
Input slew rate
SLr1(i)
160 to 410
Cycle-to-cycle period jitter
t(Ø)dyn
Half-period jitter
tjit(hper)
Output to Output Skew
tskew
Dynamic Phase Offset


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