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P4C150-25DC Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C150-25DC Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 11 page P4C150 Page 5 of 11 Document # SRAM105 REV A TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(10) 12. Write Cycle Time is measured from the last valid address to the first transition address. Notes: 10. CS and WE must be LOW for WRITE cycle. 11. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state. TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CS CS CS CS CONTROLLED)(10) Sym. t WC t CW t AW t AS t WP t AH t DW t DH t WZ t OW Parameter Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write -10 Min 10 8 8 0 8 0 5 0 2 Max 5 -12 Min 12 10 10 1 10 1 8 1 2 Max 8 -15 Min 15 11 13 1 11 1 11 1 2 Max 12 -20 Min 20 13 16 1 13 1 13 1 3 Max 15 -25 Min 25 15 20 2 15 2 15 2 3 Max 20 AC CHARACTERISTICS—WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) -35 Min 35 20 25 2 20 2 20 2 3 Max 25 Unit ns ns ns ns ns ns ns ns ns ns Write Cycle Time |
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