64K x 1 Static RAM
CY7C187
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05044 Rev. *A
Revised July 24, 2006
Features
•High speed
—15 ns
• CMOS for optimum speed/power
• Low active power
—495 mW
• Low standby power
—110 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 22-pin (300-Mil)
Molded DIP and 24-pin (300-Mil) Molded SOJ
Functional Description
The CY7C187 is a high-performance CMOS static RAM
organized as 65,536 words x 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and tri-state
drivers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pin will appear on the data output
(DOUT) pin.
The output pin stays in high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Selection Guide
-15
-25
-35
Maximum Access Time (ns)
15
25
35
Maximum Operating Current (mA)
90
70
70
Maximum CMOS Standby Current (mA)
20
20
20
Logic Block Diagram
Pin Configurations
ARRAY
C187–1
A12
A13
A14
A15
A0
A1
A2
A3
COLUMN DECODER
INPUT BUFFER
POWER
DOWN
DI
DO
CE
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
19
22
21
20
Top View
DIP
A0
A1
A2
A3
A4
DOUT
WE
GND
CE
VCC
A15
A14
A13
A12
A10
A9
A8
DIN
A11
C187–2
WE
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
A0
A1
A2
A3
A4
NC
CE
VCC
A15
A14
A13
A12
A10
A9
A8
DIN
NC
GND
DOUT
12
13
C187–3
A5
A6
A7
A11
A5
A6
A7
16K x 1
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