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CY7C106D Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C106D
Description  1-Mbit (256K x 4) Static RAM
Download  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C106D Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *E
Page 5 of 11
Switching Characteristics (Over the Operating Range) [6]
Parameter
Description
7C106D-10
7C1006D-10
Unit
Min
Max
Read Cycle
tpower [7]
VCC(typical) to the first access
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
10
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
10
ns
tDOE
OE LOW to Data Valid
5
ns
tLZOE
OE LOW to Low Z
0
ns
tHZOE
OE HIGH to High Z [8, 9]
5ns
tLZCE
CE LOW to Low Z [9]
3ns
tHZCE
CE HIGH to High Z [8, 9]
5ns
tPU [10]
CE LOW to Power-Up
0
ns
tPD [10]
CE HIGH to Power-Down
10
ns
Write Cycle [11, 12]
tWC
Write Cycle Time
10
ns
tSCE
CE LOW to Write End
7
ns
tAW
Address Set-Up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-Up to Write End
6
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z [9]
3ns
tHZWE
WE LOW to High Z [8, 9]
5ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs
enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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