PRELIMINARY
CY7B9945V
Document Number: 38-07336 Rev. *F
Page 4 of 11
Block Diagram Description
The PLL adjusts the phase and the frequency of its output signal
to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These inputs
enable the use of either differential LVPECL or single ended
LVTTL inputs. To configure as single ended LVTTL inputs, leave
the complementary pin open (internally pulled to 1.5V), then the
other input pin is used as a LVTTL input. The REF inputs are also
tolerant to hot insertion.
The REF inputs are changed dynamically. When changing from
one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (tMIN =
tREF (nominal reference period) – tCCJ (cycle-cycle jitter) –
tPDEV (max. period deviation)) while reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in Table 1. For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation determines the tU value
as follows:
tU = 1/(fNOM*N).
N is a multiplication factor that is determined by the FS setting.
fNOM is nominal frequency of the device. N is defined in Table 2.
Divide and Phase Select Matrix
The Divide Select Matrix is comprised of three independent
banks: two of clock outputs and one for feedback. The Phase
Select Matrix, enables independent phase adjustments on
1Q[0:1], 1Q[2:3] and 2Q[0:5]. The frequency of 1Q[0:3] is
controlled by 1DS[0:1] while the frequency of 2Q[0:5] is
controlled by 2DS[0:1]. The phase of 1Q[0:1] is controlled by
1F[0:1], that of 1Q[2:3] is controlled by 1F[2:3] and that of 2Q[0:5]
is controlled by 2F[0:1].
The high fanout feedback output buffer (QF) connects to the
feedback input (FBK).This feedback output has one phase
function select input (FBF0) and two divider function selects
FBDS[0:1].
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for each
bank are shown in Table 4.
Figure 1 shows the timing relationship of programmable skew
outputs. All times are measured with respect to REF with the
output used for feedback programmed with 0tU skew. The PLL
naturally aligns the rising edge of the FB input and REF input. If
the output used for feedback is programmed to another skew
position, then the whole tU matrix shifts with respect to REF. For
example, if the output used for feedback is programmed to shift
–4tU, then the whole matrix is shifted forward in time by 4tU.
Thus an output programmed with 4tU of skew gets effectively be
skewed 8tU with respect to REF.
Table 1. Frequency Range Select
FS[1]
fNOM (MHz)
Min
Max
LOW
24
52
MID
48
100
HIGH
96
200
Table 2. N Factor Determination
FS
CY7B9945V
NfNOM (MHz) at which tU = 1.0 ns
LOW
32
31.25
MID
16
62.5
HIGH
8
125
Table 3. Output Phase Select
Control Signal
Output Phase Function
1F1
1F0
1Q[0:1]
1F3
1F2
1Q[2:3]
2F1
2F0
2Q[0:5]
FBF0
QF
LOW
LOW
–4tU
–4tU
–8tU
–4tU
LOW
MID
–3tU
–3tU
–7tU
N/A
LOW
HIGH
–2tU
–2tU
–6tU
N/A
MID
LOW
–1tU
–1tU
BK1Q[0:1][2]
N/A
MID
MID
0tU
0tU
0tU
0tU
MID
HIGH
+1tU
+1tU
BK1Q[2:3][2]
N/A
HIGH
LOW
+2tU
+2tU
+6tU
N/A
HIGH
MID
+3tU
+3tU
+7tU
N/A
HIGH
HIGH
+4tU
+4tU
+8tU
+4tU
Table 4. Output Divider Select
Control Signal
Output Divider Function
[1:2]DS1
and FBDS1
[1:2]DS0
and
FBDS0
Bank1
Bank2
Feedback
LOW
LOW
/ 1
/ 1
/ 1
LOW
MID
/ 2
/ 2
/ 2
LOW
HIGH
/ 3
/ 3
/ 3
MID
LOW
/ 4
/ 4
/ 4
MID
MID
/ 5
/ 5
/ 5
MID
HIGH
/ 6
/ 6
/ 6
HIGH
LOW
/ 8
/ 8
/ 8
HIGH
MID
/ 10
/ 10
/ 10
HIGH
HIGH
/ 12
/ 12
/ 12
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