7

ICS97ULPA877A

1088B—01/18/06

Notes:

1.

Switching characteristics guaranteed for application frequency range.

2.

Static phase offset shifted by design.

Switching Characteristics

1

PARAMETER

SYMBOL

CONDITION

(MHz)

MIN

TYP

MAX

UNITS

Output enable time

OE to any output

4.73

8

ns

Output disable time

OE to any output

5.82

8

ns

160 to 270

-40

40

ps

271 to 410

-30

30

ps

160 to 270

-60

60

ps

271 to 410

-50

50

ps

Input Clock

1

2.5

4

v/ns

Output Enable (OE), (OS)

0.5

v/ns

Output clock slew rate

SLr1(o)

1.5

2.5

3

v/ns

040

ps

0

-40

ps

160 to 270

-50

50

ps

271 to 410

-20

20

ps

Static Phase Offset

2

271 to 410

-50

0

50

ps

80

ps

∑

t (h)

60

ps

160 to 270

40

ps

271 to 410

30

ps

SSC modulation frequency

30.00

33

kHz

SSC clock input frequency

deviation

0.00

-0.50

%

PLL Loop bandwidth (-3 dB

from unity gain)

2.0

MHz

Output to Output Skew

160 to 410

Period jitter

Input slew rate

SLr1(i)

160 to 410

Cycle-to-cycle period jitter

Dynamic Phase Offset

Half-period jitter