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IDT7164LS Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7164LS Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 11 page  6.42 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges 7 Timing Waveform of Read Cycle No. 1(1) NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. Timing Waveform of Read Cycle No. 2(1,2,4) Timing Waveform of Read Cycle No. 3(1,3,4) ADDRESS CS1 OE DATAOUT CS2 tRC tAA tOH tACS2 tCLZ2(5) tOE tACS1 tCLZ1(5) tOLZ (5) tCHZ2 (5) tOHZ (5) tCHZ1 (5) DATA VALID 2967 drw 05 2967 drw 06 ADDRESS DATAOUT tRC tAA tOH tOH DATA VALID DATAOUT tACS2 (5) CS1 CS2 tCLZ2 tACS1 (5) tCLZ1 tPU tPD ICC ISB tCHZ2 (5) tCHZ1 (5) DATA VALID POWER SUPPLY CURRENT 2967 drw 07 |
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