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HSDL-3603 Datasheet(PDF) 16 Page - Agilent(Hewlett-Packard)

Part # HSDL-3603
Description  IrDA짰 Data Compliant 4 Mbit/s Infrared Transceiver
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HSDL-3603 Datasheet(HTML) 16 Page - Agilent(Hewlett-Packard)

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Appendix B: PCB Layout Suggestion
The following PCB layout guide-
lines should be followed to obtain a
good PSRR and EM immunity,
resulting in good electrical
performance. Things to note:
1. The AGND pin should be
connected to the ground plane.
2. C1 and C2 are optional supply
filter capacitors; they may be left
out if a clean power supply is
used.
3. VLED can be connected to either
unfiltered or unregulated power
supply. If VLED and VCC share
the same power supply and C1 is
used, the connection should be
before the current limiting
resistor R1. In a noisy environ-
ment, including capacitor C2 can
enhance supply rejection. C1 is
generally a ceramic capacitor of
low inductance providing a wide
frequency response while C2 is a
tantalum capacitor of big volume
and fast frequency response. The
use of a tantalum capacitor is
more critical on the VLED line,
which carries a high current.
4. Preferably, a multi-layered board
should be used to provide
sufficient ground plane. Use the
layer underneath and near the
transceiver module as VCC, and
sandwich that layer between
ground connected board layers.
Refer to the diagram below for
an example of a 4-layer board.
TOP LAYER
CONNECT THE METAL SHIELD AND MODULE
GROUND PIN TO BOTTOM GROUND LAYER.
LAYER 2
CRITICAL GROUND PLANE ZONE. DO NOT
CONNECT DIRECTLY TO THE MODULE
GROUND PIN.
LAYER 3
KEEP DATA BUS AWAY FROM CRITICAL
GROUND PLANE ZONE.
BOTTOM LAYER (GND)
The area underneath the module at
the second layer, and 3 cm in all
directions around the module, is
defined as the critical ground plane
zone. The ground plane should be
maximized in this zone. Refer to
application note AN1114 or the
Agilent IrDA Data Link Design
Guide
for details. The layout below
is based on a 2-layer PCB.
28 mm
Top Layer
Figure 20. PCB layout suggestion.
Bottom Layer
17.2 mm


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