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89HPES24NT3 Datasheet(PDF) 2 Page - Integrated Device Technology |
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89HPES24NT3 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 31 page  2 of 31 April 11, 2007 IDT 89HPES24NT3 Data Sheet *Notice: The information in this document is subject to change without notice ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twenty-four 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Upstream port can be dynamically swapped with non-trans- parent downstream port to support failover applications – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC pass-through in transparent and non-trans- parent ports – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) – Unused SerDes are disabled ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is also used by an external Hot-Plug I/O expander – Master and slave interfaces may be tied together so the switch can act as both master and slave ◆ Eight General Purpose Input/Output pins ◆ Packaged in 27x27mm 420-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES24NT3 provides the most efficient high-performance I/O connectivity solution for applica- tions requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-trans- parent bridging, the PES24NT3, as a standalone switch or as a chipset with IDT PCIe System Interconnect Switches, enables multi-host and intelligent I/O applications requiring inter-domain communication. The PES24NT3 provides 96 Gbps (12 GBps) of aggregated, full-duplex switching capacity through 24 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specifica- tion 1.0a. The PES24NT3 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.0a. The PES24NT3 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management. This includes round robin port arbitration, guar- anteeing bandwidth allocation and/or latency for critical traffic classes in applications such as high throughput 10 GbE I/Os, SATA controllers, and Fibre Channel HBAs. Switch Configuration The PES24NT3 is a three port switch that contains 24 PCI Express lanes. Each of the three ports is statically allocated 8 lanes with ports labeled as A, B and C. Port A is the upstream port, port B is the trans- parent downstream port, and port C is the non-transparent downstream port. During link training, link width is automatically negotiated. Each PES24NT3 port is capable of independently negotiating to a x8, x4, x2 or x1 width. Thus, the PES24NT3 may be used in virtually any three port switch configuration (e.g., {x8, x8, x8}, {x4, x4, x4}, {x4, x2, x1}, etc.). The PES24NT3 supports static lane reversal. For example, lane reversal for upstream port A may be configured by asserting the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for ports B and C may be enabled via a configuration space register, serial EEPROM, or the SMBus. |
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