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89HPES48T12 Datasheet(PDF) 5 Page - Integrated Device Technology |
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89HPES48T12 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 47 page  5 of 47 July 19, 2007 IDT 89HPES48T12 Data Sheet PE7TP[3:0] PE7TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. PE8RP[3:0] PE8RN[3:0] I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for port 8. PE8TP[3:0] PE8TN[3:0] O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for port 8. PE9RP[3:0] PE9RN[3:0] I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs for lanes 4 through 7. PE9TP[3:0] PE9TN[3:0] O PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs for lanes 4 through 7. PE10RP[3:0] PE10RN[3:0] I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for port 10. PE10TP[3:0] PE10TN[3:0] O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs for port 10. PE11RP[3:0] PE11RN[3:0] I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for port 11. When port 10 is merged with port 11, these signals become port 10 receive pairs for lanes 4 through 7. PE11TP[3:0] PE11TN[3:0] O PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs for port 11. When port 10 is merged with port 11, these signals become port 10 trans- mit pairs for lanes 4 through 7. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz REFCLKP[3:0] REFCLKN[3:0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 3 SMBus Interface Pins (Part 1 of 2) Signal Type Name/Description Table 2 PCI Express Interface Pins (Part 2 of 2) |
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