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July 19, 2007

IDT 89HPES32H8 Data Sheet

Pin Description

The following tables lists the functions of the pins provided on the PES32H8. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ-

ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal

ending in “N” is the negative portion of the differential pair.

Signal

Type

Name/Description

PE0RP[3:0]

PE0RN[3:0]

I

PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for

port 0. Port 0 is the upstream port.

PE0TP[3:0]

PE0TN[3:0]

O

PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for

port 0. Port 0 is the upstream port.

PE1RP[3:0]

PE1RN[3:0]

I

PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for

port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs

for lanes 4 through 7.

PE1TP[3:0]

PE1TN[3:0]

O

PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for

port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs

for lanes 4 through 7.

PE2RP[3:0]

PE2RN[3:0]

I

PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for

port 2.

PE2TP[3:0]

PE2TN[3:0]

O

PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for

port 2.

PE3RP[3:0]

PE3RN[3:0]

I

PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for

port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs

for lanes 4 through 7.

PE3TP[3:0]

PE3TN[3:0]

O

PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for

port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs

for lanes 4 through 7.

PE4RP[3:0]

PE4RN[3:0]

I

PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for

port 4.

PE4TP[3:0]

PE4TN[3:0]

O

PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for

port 4.

PE5RP[3:0]

PE5RN[3:0]

I

PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for

port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs

for lanes 4 through 7.

PE5TP[3:0]

PE5TN[3:0]

O

PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for

port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs

for lanes 4 through 7.

PE6RP[3:0]

PE6RN[3:0]

I

PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for

port 6.

PE6TP[3:0]

PE6TN[3:0]

O

PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for

port 6.

PE7RP[3:0]

PE7RN[3:0]

I

PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for

port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs

for lanes 4 through 7.

Table 2 PCI Express Interface Pins (Part 1 of 2)