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ICS8535I-31 Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS8535I-31 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 15 page ICS8535I-31 LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER IDT™ / ICS™3.3V LVPECL FANOUT BUFFER 10 ICS8535AGI-31 REV. A AUGUST 16, 2007 Power Considerations This section provides information on power dissipation and junction temperature for the ICS8535I-31. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535I-31 is the sum of the core power plus the power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 65mA = 225.2mW • Power (outputs)MAX = 30mW/Loaded Output Pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 225.2mW + 120mW = 345.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air flow of 200 linear feet per meter and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.345W * 66.6°C/W = 108°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θ JA by Velocity Linear Feet per minute 0200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. |
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