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ICS873991AY-147LF Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS873991AY-147LF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 17 page IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR 10 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY LVPECL CLOCK INPUT INTERFACE The PCLK/nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and VOH must meet the V PP and V CMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER HiPerClockS PCLK nPCLK PCLK/nPCLK 3.3V R2 50 R1 50 3.3V Zo = 50 Ohm CML 3.3V Zo = 50 Ohm 3.3V HiPerClockS PCLK nPCLK R2 84 R3 125 Input Zo = 50 Ohm R4 125 R1 84 LVPECL 3.3V 3.3V Zo = 50 Ohm C2 R2 1K R5 100 Zo = 50 Ohm 3.3V 3.3V C1 R3 1K LVDS R4 1K HiPerClockS PCLK nPCLK R1 1K Zo = 50 Ohm 3.3V PC L K /n PC LK 3.3V R5 100 - 200 3.3V 3.3V HiPerClockS PCLK nPCLK R1 125 PCLK/nPCLK R2 125 R3 84 C1 C2 Zo = 50 Ohm R4 84 Zo = 50 Ohm R6 100 - 200 3.3V LVPECL FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 3.3V CML Built-In Pullup R1 100 PCLK nPCLK HiPerClockS PCLK/nPCLK Zo = 50 Ohm Zo = 50 Ohm FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER |
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