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PM3386-BI Datasheet(PDF) 4 Page - PMC-Sierra, Inc |
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PM3386-BI Datasheet(HTML) 4 Page - PMC-Sierra, Inc |
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4 / 315 page  RELEASED PM3386 DATASHEET PMC-1991129 ISSUE 7 DUAL GIGABIT ETHERNET CONTROLLER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10.2.6 EGMAC ADDRESS FILTER LOGIC ................................. 48 10.3 MANAGEMENT STATISTICS (MSTAT) ...................................... 48 10.4 POS-PHY LEVEL 3 PHYSICAL LAYER INTERFACE ................. 49 10.4.1 POS-PHY LEVEL 3 GENERAL ........................................ 49 10.4.2 POS-PHY LEVEL 3 INGRESS PHYSICAL LAYER INTERFACE (PL3IP) ........................................................ 49 10.4.3 POS-PHY LEVEL 3 EGRESS PHYSICAL LAYER INTERFACE (PL3EP)....................................................... 50 10.5 MICROPROCESSOR INTERFACE ............................................ 51 10.6 JTAG TEST ACCESS PORT INTERFACE.................................. 51 11 NORMAL MODE REGISTER DESCRIPTION ....................................... 52 12 TEST FEATURES DESCRIPTION ...................................................... 234 12.1 JTAG TEST PORT .................................................................... 235 13 OPERATION ........................................................................................ 236 13.1 POWER ON SEQUENCE ......................................................... 236 13.2 SYSTEM RESET....................................................................... 236 13.3 GMII VS. SERDES CONFIGURATION ..................................... 237 13.4 SYSTEM CLOCKING................................................................ 237 13.4.1 PHY-LINK FREQUENCY SELECTION........................... 237 13.4.2 GMII MODE CLOCKING ................................................ 237 13.4.3 SERDES MODE CLOCKING ......................................... 238 13.5 INTERFACING TO ODL ............................................................ 238 13.6 GMII INTERFACING ................................................................. 239 13.7 TBI INTERFACING.................................................................... 240 13.8 ENABLING AND DISABLING DATA FLOWS ............................ 241 |
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