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CS8416-DSZR Datasheet(PDF) 45 Page - Cirrus Logic

Part # CS8416-DSZR
Description  192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8416-DSZR Datasheet(HTML) 45 Page - Cirrus Logic

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45
CS8416
14.16 OMCK/RMCK Ratio (18h)
This register allows the calculation of the incoming sample rate by the host microcontroller from the equation
ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256*Fso. ORR is rep-
resented as an unsigned 2-bit integer and a 6-bit fractional part. The value is meaningful only after the PLL
has reached lock. For example, if the OMCK is 12.288 MHz, Fso would be 48 kHz (48 kHz =
12.288 MHz/256). Then, if the input sample rate is also 48 kHz, you would get 1.0 from the ORR register
(The value from the ORR register is hexadecimal, so the actual value you will get is 40h).
If FSO/FSI > 3 63/64, ORR will saturate at the value FFh. Also, there is no hysteresis on ORR. Therefore a
small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.
ORR[7:6]
- Integer part of the ratio (Integer value=Integer(SRR[7:6])).
ORR[5:0]
- Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64).
14.17 Channel Status Registers (19h - 22h)
14.18 IEC61937 PC/PD Burst Preamble (23h - 26h)
14.19 CS8416 I.D. and Version Register (7Fh)
ID[3:0]
- ID code for the CS8416. Permanently set to 0010
VER[3:0]
= 0001 (revision A)
VER[3:0]
= 0010 (revision B)
VER[3:0]
= 0011 (revision C)
VER[3:0
] = 0111 (revision D)
VER[3:0]
= 1111 (revision E)
76543210
ORR7
ORR6
ORR5
ORR4
ORR3
ORR2
ORR1
ORR0
19h
Channel A Status Byte 0
AC0[7]
AC0[6]
AC0[5]
AC0[4]
AC0[3]
AC0[2]
AC0[1]
AC0[0]
1Ah
Channel A Status Byte 1
AC1[7]
AC1[6]
AC1[5]
AC1[4]
AC1[3]
AC1[2]
AC1[1]
AC1[0]
1Bh
Channel A Status Byte 2
AC2[7]
AC2[6]
AC2[5]
AC2[4]
AC2[3]
AC2[2]
AC2[1]
AC2[0]
1Ch
Channel A Status Byte 3
AC3[7]
AC3[6]
AC3[5]
AC3[4]
AC3[3]
AC3[2]
AC3[1]
AC3[0]
1Dh
Channel A Status Byte 4
AC4[7]
AC4[6]
AC4[5]
AC4[4]
AC4[3]
AC4[2]
AC4[1]
AC4[0]
1Eh
Channel B Status Byte 0
BC0[7]
BC0[6]
BC0[5]
BC0[4]
BC0[3]
BC0[2]
BC0[1]
BC0[0]
1Fh
Channel B Status Byte 1
BC1[7]
BC1[6]
BC1[5]
BC1[4]
BC1[3]
BC1[2]
BC1[1]
BC1[0]
20h
Channel B Status Byte 2
BC2[7]
BC2[6]
BC2[5]
BC2[4]
BC2[3]
BC2[2]
BC2[1]
BC2[0]
21h
Channel B Status Byte 3
BC3[7]
BC3[6]
BC3[5]
BC3[4]
BC3[3]
BC3[2]
BC3[1]
BC3[0]
22h
Channel B Status Byte 4
BC4[7]
BC4[6]
BC4[5]
BC4[4]
BC4[3]
BC4[2]
BC4[1]
BC4[0]
23h
Burst Preamble PC Byte 0
PC0[7]
PC0[6]
PC0[5]
PC0[4]
PC0[3]
PC0[2]
PC0[1]
PC0[0]
24h
Burst Preamble PC Byte 1
PC1[7]
PC1[6]
PC1[5]
PC0[4]
PC1[3]
PC1[2]
PC1[1]
PC1[0]
25h
Burst Preamble PD Byte 0
PD0[7]
PD0[6]
PD0[5]
PC0[4]
PD0[3]
PD0[2]
PD0[1]
PD0[0]
26h
Burst Preamble PD Byte 1
PD1[7]
PD1[6]
PD1[5]
PD1[4]
PD1[3]
PD1[2]
PD1[1]
PD1[0]
76543210
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0


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