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CS8421-CNZ Datasheet(PDF) 24 Page - Cirrus Logic

Part # CS8421-CNZ
Description  32-bit, 192 kHz Asynchronous Sample Rate Converter
Download  38 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8421-CNZ Datasheet(HTML) 24 Page - Cirrus Logic

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24
DS641F1
CS8421
4.5
Reset, Power-Down, and Start-Up
When RST is low, the CS8421 enters a low-power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high, the part senses the resistor value on the configuration pins
(MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (ap-
proximately 4
µs), the part is set to normal operation and all outputs are functional.
4.6
Power Supply, Grounding, and PCB Layout
The CS8421 operates from a VD = +2.5 V and VL = +3.3 V or +5.0 V supply. These supplies may be set
independently. Follow normal supply decoupling practices; see Figure 6.
Extensive use of power and ground planes, ground-plane fill in unused areas, and surface-mount decou-
pling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the
board as the CS8421 to minimize inductance effects, and all decoupling capacitors should be as close to
the CS8421 as possible. The pin of the configuration resistors not connected to MS_SEL, SAIF, and SAOF
should be connected as close as possible to VL or GND.
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TDM_IN
OLRCK
OSCLK
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
Output
Clock
Source
LRCK
SCLK
OLRCK
OSCLK
SDOUT
PCM Source 2
OLRCK
OSCLK
SDOUT
PCM Source 1
CS84211
Slave
CS84212
Slave
LRCK
SCLK
SDIN
DSP
Slave
OLRCK
OSCLK
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
CS84213
Slave
OLRCK
OSCLK
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
CS84214
Slave
OLRCK
OSCLK
SDOUT
PCM Source 3
OLRCK
OSCLK
SDOUT
PCM Source 4
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TDM_IN
CS84211
OLRCK
OSCLK
SDOUT
PCM Source 2
OLRCK
OSCLK
SDOUT
PCM Source 1
Master
LRCK
SCLK
SDIN
DSP
Slave
OLRCK
OSCLK
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
CS84214
Slave
OLRCK
OSCLK
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
CS84212
Slave
OLRCK
OSCLK
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
CS84213
Slave
OLRCK
OSCLK
SDOUT
PCM Source 3
OLRCK
OSCLK
SDOUT
PCM Source 4
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave)


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