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PXAS33KBBE Datasheet(PDF) 7 Page - NXP Semiconductors |
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PXAS33KBBE Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 52 page Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range 2000 Dec 01 7 PIN DESCRIPTIONS MNEMONIC PIN NUMBER TYPE NAME AND FUNCTION MNEMONIC PLCC LQFP TYPE NAME AND FUNCTION VSS 1, 20, 55 12, 13, 53, 54, 69, 70 I Ground: 0 V reference. VDD 2, 21, 54 14, 15, 51, 52, 71, 72 I Power Supply: This is the power supply voltage for normal, idle, and power down operation. RST 50 47 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. RSTOUT 19 11 O Reset Output: This pin outputs a low whenever the XA-S3 processor is reset for any reason. This includes an external reset via the RST pin, watchdog reset, and the RESET instruction. ALE/PROG 47 44 I/O Address Latch Enable/Program Pulse: A high output on the ALE pin signals external circuitry to latch the address portion of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order to process a bus cycle. PSEN 48 45 O Program Store Enable: The read strobe for external program memory. When the microcontroller accesses external program memory, PSEN is driven low in order to enable memory devices. PSEN is only active when external code accesses are performed. EA/WAIT/VPP 22 16 I External Access/Bus Wait: The EA input determines whether the internal program memory of the microcontroller is used for code execution. The value on the EA pin is latched as the external reset input is released and applies during later execution. When latched as a 0, external program memory is used exclusively. When latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. After reset is released, this pin takes on the function of bus WAIT input. If WAIT is asserted high during an external bus access, that cycle will be extended until WAIT is released. XTAL1 68 68 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. XTAL2 67 67 I Crystal 2: Output from the oscillator amplifier. CLKOUT 49 46 O Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output may be disabled by software. AVDD 33 28, 29 I Analog Power Supply: Positive power supply input for the A/D converter. AVSS 34 30, 31 I Analog Ground. AVREF+ 32 27 I A/D Positive Reference Voltage: High end reference for the A/D converter. AVREF– 31 26 I A/D Negative Reference Voltage: Low end reference for the A/D converter. P0.0 – P0.7 45, 46, 51–53, 56–58 42, 43, 48–50, 55–57 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11. |
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