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XA-SCC Datasheet(PDF) 16 Page - NXP Semiconductors |
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XA-SCC Datasheet(HTML) 16 Page - NXP Semiconductors |
16 / 42 page Philips Semiconductors Preliminary specification XA-SCC CMOS 16-bit communications microcontroller 1999 Mar 29 16 MMR Name Reset Value Description Address Offset Size Read/Write or Read Only SCP Interface Registers SCPCFG R/W 8 260h SCP Configuration 8xh SCPD R/W 8 262h SCP Data Byte xx SCPCS R/W 8 263h SCP Control & Status 00h Autobaud Registers BDAEE R/W 8 270h Autobaud Echo Enable 00h .. BDCS R/W 8 272h Autobaud Control & Status 00h .. Memory Interface (MIF) Registers B0CFG R/W 8 280h MIF Bank 0 Config — B0AM R/W 8 281h MIF Bank 0 Base Address 00h.. B0TMG R/W 8 282h MIF Bank 0 Timing Params — B1CFG R/W 8 284h MIF Bank 1 Config 0xh B1AM R/W 8 285h MIF Bank 1 Base Address xxh B1TMG R/W 8 286h MIF Bank 1 Timing Params xxh B2CFG R/W 8 288h MIF Bank 2 Config 0xh B2AM R/W 8 289h MIF Bank 2 Base Address xx B2TMG R/W 8 28Ah MIF Bank 2 Timing Params xx B3CFG R/W 8 28Ch MIF Bank 3 Config 0xh B3AM R/W 8 28Dh MIF Bank 3 Base Address xx B3TMG R/W 8 28Eh MIF Bank 3 Timing Params xx B4CFG R/W 8 290h MIF Bank 4 Config 0xh B4AM R/W 8 291h MIF Bank 4 Base Address xx B4TMG R/W 8 292h MIF Bank 4 Timing Params xx B5CFG R/W 8 294h MIF Bank 5 Config 0xh B5AM R/W 8 295h MIF Bank 5 Base Address xx B5TMG R/W 8 296h MIF Bank 5 Timing Params xx MBCL R/W 8 2BEh MIF Memory Bank Configuration Lock Register 3Fh RFSH R/W 8 2BFh MIF Refresh Control 00h IDL Interface Registers MSI Control Register R/W 16 2C0h IDL Mode Control Register 0000h DataMask Register R/W 16 2C2h IDL Mask Register 0000h Miscellaneous Registers Hi-Pri Soft Ints & Pin Mux Control Reg. R/W 16 2D0h Control bits for Hi-Priority Soft Ints, and Pin Mux 0000h XInt2 R/W 8 2D2h External Interrupt 2 Control 00h |
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