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XA-G49 Datasheet(PDF) 6 Page - NXP Semiconductors

Part # XA-G49
Description  XA 16-bit microcontroller family 64K FLASH/2K RAM, watchdog, 2 UARTs
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

XA-G49 Datasheet(HTML) 6 Page - NXP Semiconductors

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Philips Semiconductors
Preliminary specification
XA-G49
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
2000 Apr 03
6
MNEMONIC
NAME AND FUNCTION
TYPE
PIN. NO.
MNEMONIC
NAME AND FUNCTION
TYPE
LQFP
LCC
PSEN
32
26
O
Program Store Enable: The read strobe for external program memory. When the microcontroller
accesses external program memory, PSEN is driven low in order to enable memory devices. PSEN
is only active when external code accesses are performed.
EA/WAIT/
VPP
35
29
I
External Access/Wait/Programming Supply Voltage: The EA input determines whether the
internal program memory of the microcontroller is used for code execution. The value on the EA pin
is latched as the external reset input is released and applies during later execution. When latched
as a 0, external program memory is used exclusively, when latched as a 1, internal program
memory will be used up to its limit, and external program memory used above that point. After reset
is released, this pin takes on the function of bus Wait input. If Wait is asserted high during any
external bus access, that cycle will be extended until Wait is released. During EPROM
programming, this pin is also the programming supply voltage input.
XTAL1
21
15
I
Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock
generator circuits.
XTAL2
20
14
O
Crystal 2: Output from the oscillator amplifier.
SPECIAL FUNCTION REGISTERS
NAME
DESCRIPTION
SFR
ADDRESS
BIT FUNCTIONS AND ADDRESSES
RESET
NAME
DESCRIPTION
SFR
ADDRESS
MSB
LSB
VALUE
AUXR
Auxiliary function register
44C
ENBOOT
FMIDLE
PWR_VLD
BCR
Bus configuration register
46A
WAITD
BUSD
BC2
BC1
BC0
Note 1
BTRH
Bus timing register high byte
469
DW1
DW0
DWA1
DWA0
DR1
DR0
DRA1
DRA0
FF
BTRL
Bus timing register low byte
468
WM1
WM0
ALEW
CR1
CR0
CRA1
CRA0
EF
CS
Code segment
443
00
DS
Data segment
441
00
ES
Extra segment
442
00
33F
33E
33D
33C
33B
33A
339
338
IEH*
Interrupt enable high byte
427
ETI1
ERI1
ETI0
ERI0
00
337
336
335
334
333
332
331
330
IEL*
Interrupt enable low byte
426
EA
ET2
ET1
EX1
ET0
EX0
00
IPA0
Interrupt priority 0
4A0
PT0
PX0
00
IPA1
Interrupt priority 1
4A1
PT1
PX1
00
IPA2
Interrupt priority 2
4A2
PT2
00
IPA4
Interrupt priority 4
4A4
PTI0
PRI0
00
IPA5
Interrupt priority 5
4A5
PTI1
PRI1
00
387
386
385
384
383
382
381
380
P0*
Port 0
430
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FF
38F
38E
38D
38C
38B
38A
389
388
P1*
Port 1
431
T2EX
T2
TxD1
RxD1
A3
A2
A1
WRH
FF
397
396
395
394
393
392
391
390
P2*
Port 2
432
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
FF
39F
39E
39D
39C
39B
39A
399
398
P3*
Port 3
433
RD
WR
T1
T0
INT1
INT0
TxD0
RxD0
FF


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