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XA-C3 Datasheet(PDF) 20 Page - NXP Semiconductors |
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XA-C3 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 68 page  Philips Semiconductors Preliminary specification XA-C3 XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor 2000 Jan 25 13 New Enhanced Mode 0 For timers T0 or T1 the 13–bit count mode on the 80C51 (current Mode 0) has been replaced in the XA with a 16–bit auto–reload mode. Four additional 8–bit data registers (two per timer: RTHn and RTLn) are created to hold the auto–reload values. In this mode, the TH overflow will set the TF flag in the TCON register (see Figure 7) and cause both the TL and TH counters to be loaded from the RTL and RTH registers respectively. These new SFRs will also be used to hold the TL reload data in the 8–bit auto–reload mode (Mode 2) instead of TH. The overflow rate for Timer 0 or Timer 1 in Mode 0 may be calculated as follows: Timer_Rate = fosc / (N * (65536 – Timer_Reload_Value)) where N = the TCLK prescaler value: 4 (default), 16, or 64. Mode 1 Mode 1 is the 16–bit non–auto reload mode. Mode 2 Mode 2 configures the Timer register as an 8–bit Counter (TLn) with automatic reload. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of RTLn, which is preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer/Counter 0. The overflow rate for Timer 0 or Timer 1 in Mode 2 may be calculated as follows: Timer_Rate = fosc / (N * (256 – Timer_Reload_Value)) where N = the TCLK prescaler value: 4, 16, or 64. Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. TL0 uses the Timer 0 control bits: C0 ; T0/, GATE0, TR0, INT0/ and TF0. TH0 is locked into a timer function and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications requiring an extra 8–bit timer. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. IT0 LSB MSB BIT SYMBOL FUNCTION TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. This flag will not be set if T1OE (TSTAT.2) is set. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. This flag will not be set if T0OE (TSTAT.0) is set. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.2 IT1 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. SU00604C IE0 IT1 IE1 TR0 TF0 TR1 TF1 TCON Address:410 Bit Addressable Reset Value: 00H Figure 7. Timer/Counter Control (TCON) Register |
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