LH79520N0Q000B1 datasheet(5/59 Pages) NXP | System-on-Chip

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LH79520N0Q000B1 Datasheet(PDF) 5 Page - NXP Semiconductors

Part #	LH79520N0Q000B1

Description	System-on-Chip

Download	59 Pages

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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System-on-Chip

LH79520

Preliminary data sheet

Rev. 01 — 16 July 2007

5

NXP Semiconductors

SIGNAL DESCRIPTIONS

Table 2. LH79520 Signal Descriptions

PIN NO.

SIGNAL NAME

TYPE

DESCRIPTION

NOTES

MEMORY INTERFACE (MI)

2-7

9-12

14-17

19-22

24-27

29-32

A[25:0]

Output

Address Signals

50-54

56-63

65-66

67-69

71-74

76-79

81-84

86-87

D[31:0]

Input/Output

Data Input/Output Signals

1

101

SDCLK

Output

SDRAM Clock

1

109

DQM3

Output

Data Mask Output to SDRAMs

1

110

DQM2

Output

Data Mask Output to SDRAMs

1

111

DQM1

Output

Data Mask Output to SDRAMs

1

112

DQM0

Output

Data Mask Output to SDRAMs

1

102

SDCKE

Output

SDRAM Clock Enable

1

104

nDCS1

Output

SDRAM Chip Select

1

105

nDCS0

Output

SDRAM Chip Select

1

107

nRAS

Output

Row Address Strobe

108

nCAS

Output

Column Address Strobe

106

nSDWE

Output

SDRAM Write Enable

1

41

nCS6

Output

Static Memory Controller Chip Select

1

42

nCS5

Output

Static Memory Controller Chip Select

1

43

nCS4

Output

Static Memory Controller Chip Select

1

44

nCS3

Output

Static Memory Controller Chip Select

1

46

nCS2

Output

Static Memory Controller Chip Select

47

nCS1

Output

Static Memory Controller Chip Select

48

nCS0

Output

Static Memory Controller Chip Select

38

nOE

Output

Static Memory Controller Output Enable

34

nBLE3

Output

Static Memory Controller Byte Lane Enable / Byte Write Enable

1

35

nBLE2

Output

Static Memory Controller Byte Lane Enable / Byte Write Enable

1

36

nBLE1

Output

Static Memory Controller Byte Lane Enable / Byte Write Enable

37

nBLE0

Output

Static Memory Controller Byte Lane Enable / Byte Write Enable

39

nWE

Output

Static Memory Controller Write Enable

144

nWAIT

Input

Static Memory Controller External Wait Control

1, 3

DMA CONTROLLER (DMAC)

148

DEOT0

Output

DMA 0 End of Transfer

1

147

nDACK0

Output

DMA 0 Acknowledge

1

146

DREQ0

Input

DMA 0 Request

1

157

DEOT1

Output

DMA 1 End of Transfer

1

145

DACK1

Output

DMA 1 Acknowledge

1

144

DREQ1

Input

DMA 1 Request

1, 3

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