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UMA1020AM Datasheet(PDF) 4 Page - NXP Semiconductors |
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UMA1020AM Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 20 page 1995 Jul 06 4 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM PINNING SYMBOL PIN DESCRIPTION FAST 1 control input to speed-up main synthesizer CPPF 2 principal synthesizer speed-up charge-pump output CPP 3 principal synthesizer normal charge-pump output VDD1 4 digital power supply 1 VDD2 5 digital power supply 2 PRI 6 1.7 GHz principal synthesizer frequency input DGND 7 digital ground fXTAL 8 common crystal frequency input from TCXO POFF 9 principal synthesizer power-down input n.c. 10 not connected CLK 11 programming bus clock input DATA 12 programming bus data input E 13 programming bus enable input (active LOW) ISET 14 regulator pin to set the charge-pump currents AUX 15 auxiliary synthesizer frequency input AGND 16 analog ground CPA 17 auxiliary synthesizer charge-pump output VCC 18 supply for charge-pump AOFF 19 auxiliary synthesizer power-down input LOCK 20 in-lock detect output (main PLL); test mode output Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Principal synthesizer Programmable reference and main dividers drive the principal PLL phase detector. Two charge pumps produce phase error current pulses for integration in an external loop filter. A hardwired power-down input POFF (pin 9) ensures that the dividers and phase comparator circuits can be disabled. The PRI input (pin 6) drives a preamplifier to provide the clock to the first divider stage. The preamplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from 100 mV to 500 mV (RMS), and at frequencies up to 1.7 GHz. The high frequency divider circuits use bipolar transistors, slower bits are CMOS. Divider ratios (512 to 131071) allow up to 2 MHz phase comparison frequency. |
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