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CS5451A Datasheet(PDF) 5 Page - Cirrus Logic

Part # CS5451A
Description  Six-channel, Delta-sigma Analog-to-digital Converter
Download  13 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5451A Datasheet(HTML) 5 Page - Cirrus Logic

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CS5451A
DS635F2
5
ANALOG CHARACTERISTICS (continued)
Notes:
1.
Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1
2.
All outputs unloaded. All inputs CMOS level.
3.
Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using charge-
pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins.
The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words
are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this
rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq.
PSRR is then (in dB):
DIGITAL CHARACTERISTICS (See Note 4)
Min/Max characteristics and specifications are guaranteed over all Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 3V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.
XIN = 4.096 MHz
Notes:
4.
All measurements performed under static conditions.
5.
For OWRS and GAIN pins, input leakage current is 30 µA (Max).
Parameter
Symbol
Min
Typ
Max
Unit
Power Supplies
Power Supply Currents
IA+
Typical VA+=VD+=+3V; VA-=-2V
ID+ with CPD
ID+ without CPD
PSCA
PSCD
PSCD
-
-
-
4.0
5.0
1.0
5.3
6.3
1.5
mA
mA
mA
Power Consumption
With CPD
(Note 2)
Without CPD
PC
PC
-
-
27
23
35
31
mW
mW
Power Supply Rejection
(DC)
50, 60 Hz (Note 3)
Voltage Channel
50, 60 Hz (Note 3)
Current Channel
PSRR
PSRR
PSRR
50
50
60
-
65
90
-
-
-
dB
dB
dB
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Characteristics
Master Clock Frequency
XIN
3
4.096
5
MHz
Master Clock Duty Cycle
40
-
60
%
Filter Characteristics
High Rate Filter Output Word Rate
OWRS = 0
OWRS = 1
OWR
OWR
-
-
XIN/2048
XIN/1024
-
-
Hz
Hz
Input/Output Characteristics
High-Level Input Voltage
VIH
0.6 VD+
-
VD+
V
Low-Level Input Voltage
VIL
0.0
-
0.8
V
High-Level Output Voltage
Iout = -5.0 mA
VOH
(VD+) - 1.0
-
-
V
Low-Level Output Voltage
Iout = 5.0 mA
VOL
--
0.4
V
Input Leakage Current
(Note 5)
Iin
-±1
±10
µA
3-State Leakage Current
IOZ
--
±10
µA
Digital Output Pin Capacitance
Cout
-9
-
pF
PSRR
20
106.07
V
eq
------------------
⎩⎭
⎨⎬
⎧⎫
log
=


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