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89HPES3T3 Datasheet(PDF) 1 Page - Integrated Device Technology |
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89HPES3T3 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  1 of 23 September 7, 2007 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. ® Device Overview The 89HPES3T3 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports. Features ◆ High Performance PCI Express Switch – Three 2.5Gbps PCI Express lanes – Three switch ports – x1 Upstream port – Two x1 Downstream ports – Low latency cut-through switch architecture – Support for Max payload sizes up to 256 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ◆ Flexible Architecture with Numerous Configuration Options – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device configuration from serial EEPROM ◆ Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates three 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC mother- boards ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI- PM 1.2) – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Speci- fication, Revision 2.0 (ACPI) supporting active link state ◆ Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters Block Diagram Figure 1 Internal Block Diagram 3-Port Switch Core / 3 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer (Port 0) (Port 2) SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer (Port 3) 89HPES3T3 Data Sheet Advance Information* 3-Lane 3-Port PCI Express® Switch |
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