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ICSSSTUAH32868AHLF Datasheet(PDF) 9 Page - Integrated Device Technology |
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ICSSSTUAH32868AHLF Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 22 page ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 9 ICSSSTUAH32868A 7115/9 Parity and Standby Function Table Inputs1 Outputs RESET DCS0 DCS1 CLK CLK Σ of Inputs = H (D1 - D28) PAR_IN2 QERR3 HL X ↑↓ Even L H HL X ↑↓ Odd L L HL X ↑↓ Even H L HL X ↑↓ Odd H H HX L ↑↓ Even L H HX L ↑↓ Odd L L HX L ↑↓ Even H L HX L ↑↓ Odd H H HH H ↑↓ XX QERR0 4 HX X ↑↓ XX QERR0 LX or Floating X or Floating X or Floating X or Floating X or Floating X or Floating H 1 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2 PAR_IN arrives one clock cycle after the data to which it applies. 3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 4 If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM plus two clock cycles or until RESET is driven LOW. |
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