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WM8804 Datasheet(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8804 Datasheet(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 66 page  Production Data WM8804 w PD Rev 4.1 September 2007 13 When the device powers up, all power up configuration pins are configured as inputs for a minimum of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based on 27MHz and 10MHz crystal clock frequencies respectively. This enables the pins to be sampled and the device to be configured before the pins are released to their selected operating conditions. Figure 7 illustrates how SDIN is sampled. Figure 7 Pin Sampling On Power Up or Hardware Reset If the device is powered up in software control mode, all functions of the device are powered down by default and must be powered up individually by writing to the relevant bits of the PWRDN register (Table 7). In hardware control mode, all functions of the device are powered up by default. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 PLLPD 1 PLL powerdown 0 = PLL enabled 1 = PLL disabled 1 SPDIFRXP D 1 S/PDIF receiver powerdown 0 = S/PDIF receiver enabled 1 = S/PDIF receiver disabled 2 SPDIFTXPD 1 S/PDIF transmitter powerdown 0 = S/PDIF transmitter enabled 1 = S/PDIF transmitter disabled 3 OSCPD 0 Oscillator power down 0 = Power Up 1 = Power Down 4 AIFPD 0 Digital audio interface power down 0 = Power Up 1= Power Down R30 PWRDN 1Eh 5 TRIOP 0 Tri-state all outputs 0 = Outputs not tri-stated 1 = Outputs tri-stated Table 7 Power Down Register D Q ENB SDIN RSTB Power- On Reset POR_B HWMODE / SWMODE Sampling of pin value at reset to generate internal signals. |
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