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S2042B-10 Datasheet(PDF) 2 Page - Applied Micro Circuits Corporation |
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S2042B-10 Datasheet(HTML) 2 Page - Applied Micro Circuits Corporation |
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2 / 20 page  Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 2 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2042/S2043 Loopback Local loopback is supported by the chipset, and pro- vides a capability for performing offline testing of the interface to ensure the integrity of the serial channel before enabling the transmission medium. It also al- lows for system diagnostics. OVERVIEW The S2042 transmitter and S2043 receiver provide serialization and deserialization functions for block- encoded data to implement a Fibre Channel interface. Operation of the S2042/S2043 chips is straightfor- ward, as depicted in Figure 2. The sequence of operations is as follows: Transmitter 1. 10/20-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 10/20-bit parallel output The 10/20-bit parallel data handled by the S2042 and S2043 devices should be from a DC-balanced encod- ing scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit transmission characters. Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figure 5. A lock detect feature is provided on the receiver, which indicates that the PLL is locked (synchronized) to the reference clock or the data stream. S2042 TRANSMITTER FUNCTIONAL DESCRIPTION The S2042 transmitter accepts parallel input data and serializes it for transmission over fiber optic or coaxial cable media. The chip is fully compatible with the ANSI X3T11 Fibre Channel standard, and sup- ports the Fibre Channel standard's data rates of 1062, 531 and 266 Mbit/sec. The parallel input data word can be either 10 bits or 20 bits wide, depending upon DWS pin selection. A block diagram showing the basic chip operation is shown in Figure 3. Figure 3. S2042 Functional Block Diagram CONTROL LOGIC TEST D(0..19) OE1 OE0 DWS REFCLK REFSEL RATESEL 2:1 10 10 20 10 DIVIDE-BY-2 PLL CLOCK MULTIPLIER F0 = F1 X 10/20 SHIFT REGISTER TX TY TLX TLY TCLK TCLKN DIVIDE-BY-2 DQ Parallel Data In S2042 Transmitter S2043 Receiver RefClk Lock Detect RefClk RCLK Parallel Data Out Loopback Loopback Sync Serial Data TCLK Figure 2. Fibre Channel Interface Diagram |
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