Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
19
GPIO Interface (24 PINs)
PIN No.
Symbol
Type
Description
AA18, AA17, AE18,
AE17, AF18, AF17,
AC17, AD17,
AA19, AC19, AD19,
AE19, AB18, AC18,
AB17, AF19
GPIO_P0[7:0]
GPIO_P1[7:0]
I/O
General-Purpose Input/Output P0[7-0] and P1[7-0]. Those pins can be
programmed input or output individually.
AA20, AB20, AD20,
AE20, AD18, AF20,
AF21, AB19
GPIO_P2[7:0]/Addre
ss[31:24]
I/O
General-Purpose Input/Output P2[7-0] . Those pins can be programmed
input or output individually.
Address[31:24].
Ethernet Interface (24 PINs)
PIN No.
Symbol
Type
Description
L22
Link/Active
Link/Active: Link/active status
K22
Duplex
Duplex: Duplex status
J24
ISET
ISET: External resistor connecting pin for BIAS
F22
ATSTP
ATSTP: VGA and ADC testing pin for input and output (positive)
F21
ATSTN
ATSTN: VGA and ADC testing pin for input and output (negative)
K25
TXN
TXN: 10B-T/100BT transmitting output pin/ reveiving input pin (positive)
K26
TXP
TXP: 10B-T/100BT transmitting output pin/ reveiving input pin (negative)
L25
RXN
RXN: 10B-T/100BT reveiving input pin/ transmitting output pin (positive)
L26
RXP
RXP: 10B-T/100BT reveiving input pin/ transmitting output pin (negative)
J16
MDC
O
MDC: MII management data clock is sourced by the Vortex86SX to the
external PHY devices as a timing reference for the transfer of information
on the MDIO signal.
K16
MDIO
I/O
MDIO: MII management data input/output transfers control information
and status between the external PHY and the Vortex86SX.
L16
COL0
I
COL0: This pin functions as the collision detection. When the external
physical layer protocol (PHY) device detects a collision, it asserts this pin.
M21
RXC0
I
RXC0: Supports the receive clock supplied by the external PMD device.
This clock should always be active.
M18, M17,
L17, L18
RXD0_[3:0]
I
RXD0_[3:0]: Four parallel receiving data lines. This data is driven by an
external PHY attached to the media and should be synchronized with the
RXC signal.
L21
RXDV0
I
RXDV0: Data valid is asserted by an external PHY when the received
data is present on the RXD[3:0] lines and is de-asserted at the end of the
packet. This signal should be synchronized with the RXC signal.
J21
TXC0
I
TXC0: Supports the transmit clock supplied by the external PMD device.
This clock should always be active.
J18, J17,
K17, K18
TXD0_[3:0]
O
TXD0_[3:0]: Four parallel transmit data lines. This data is synchronized
to the assertion of the TXC signal and is latched by the external PHY on
the rising edge of the TXC signal.
K21
TXEN0
O
TXEN0: This pin functions as Transmit Enable. It indicates that a
transmission to an external PHY device is active on the MII port.
JTAG Interface (4 PINs)
PIN No.
Symbol
Type
Description
G6
TDO
O
TDO: JTAG Test Data Output pin.
J9
TMS
I
TMS: JTAG Test Mode Select pin.
G7
TCK
I
TCK: JTAG Test Clock Input pin.
H6
TDI
I
TDI: JTAG Test Data Input pin.
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