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UCB1500 Datasheet(PDF) 11 Page - NXP Semiconductors |
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UCB1500 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 58 page  Philips Semiconductors UCB1500 PCI to AC97 bridge/host controller Objective specification Rev. 01 — 4 February 2000 11 of 58 9397 750 06854 © Philips Electronics N.V. 2000. All rights reserved. [82]: Power Management Capabilities (read only) Table 12: Power Management Capabilities register bit description Read only Bit Description 15-11(r) PME support This 5-bit field indicates the power states in which the function may assert PME. Value is set to 11001 b if VAUX_AV = 1 to indicate PME can be asserted from D3cold and D0. If VAUX_AV = 0, this field is set to 01001b to indicate PME can be asserted from D3hot and D0. The entire setting can be overwritten by BIOS via writing to 6Ah, or an external EEPROM. If VAUX_AV = 0, bit 15 shall always be zero. If VAUX = 1, bit 15 shall reflect the setting of 6Ah, or that loaded from EEPROM. 10(r) D2 support This bit is set to ‘0’ to indicate that function does not support the D2 power management state. This setting can be overwritten by BIOS via 6Ah, or with the external EEPROM. 9(r) D1 support This bit is set to ‘0’ to indicate that function does not support the D1 power management state. This setting can be overwritten by BIOS via 6Ah, or with the external EEPROM. 8-6(r) Aux_Current These bits are set to ‘0’ for PCI-PM 1.0 compliance. For PCI-PM 1.1 compliance, these bits are overwritten by BIOS via 6Ah, or loaded from an external EEPROM to reflect the 3.3VAUX current requirement. 5(r) DSI The Device Specific Initialization bit indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. This register is set to ‘0’ to indicate that it does not require special initialization. 4(r) Reserved. 3(r) PME Clock This bit is a ‘0’, indicating that the function does not rely on the presence of the PCI clock for PME operation. 2:0(r) Version This register is set to 001b, indicating that this function complies with Rev 1.0 of the PCI Power Management Interface Specification. These bits can also be overwritten by BIOS via 6Ah, or loaded from an external EEPROM to 010b for compliance with PCI-PM 1.1. |
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