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STANDARD APPLICATION

PTH04040W

19

20

18

Margin

Down

Track

Margin

Up

12

15

9

14

11

+

+

+

1

3

5

10

13

16

17

UVLO

4

6

2

8

Inhibit

GND

GND

VoAdj

−Sense

Vo

+Sense

UDG−05085

A

B

C

C

330

µF

330

µF

1%

0.05 W

1000

µF

(Required)

7

ABSOLUTE MAXIMUM RATINGS

PTH04040W

SLTS238A – SEPTEMBER 2005 – REVISED FEBRUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

A.

B.

C.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see

the TI website at www.ti.com.

over operating free-air temperature range (unless otherwise noted)

UNIT

Signal input voltages

Track control (pin 18)

–40

°C to 85°C

Wave solder

Surface temperature of module body or pins (5

PTH04040WAH

260

temperature

seconds)

PTH04040WAS

235

Solder reflow

Surface temperature of module body or pins

temperature

PTH04040WAZ

260

Storage temperature

–40

°C to 125°C

Mechanical shock

Per Mil-STD-883D, Method 2002.3, 1 msec, 1/2 Sine, mounted

Mechanical vibration

Mil-STD-883D, Method 2007.2, 20–2000 Hz

Weight

22.5 grams

Flammability

Meets UL94V-O

(1)

During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated

maximum.

(2)

Qualification limits

2

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