2

PI6C487016

Low Skew, 1-to-16

LVCMOS/LVTTL Clock Driver

PS8741D

07/29/05

Pin Descriptions

Notes:

1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.

Number

Name

Type

Description

1, 48

Power

Core supply pins (3.3V)

2

CLK0

Input

Pulldown LVCMOS / LVTTL clock input

3, 4, 5, 6

SELA :

SELD

Input

Pullup

Controls frequency division for outputs. LVCMOS / LVTTL interface

levels. QAx:QDx

7, 8, 9, 10

ENA : END

Input

Pullup

Output enable for QAx : QDx Outputs. Active HIGH. If pin is LOW,

outputs drive low. LVCMOS / LVTTL interface levels.

11

nMR/OE

Input

Pullup

Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the outputs

to high impedance. LVCMOS / LVTTL interface levels.

12, 16, 20, 24,

28, 32, 36, 40,

44

GND

Power

Supply Ground

13, 15, 17, 19

QD0 : QD3

Output

Bank D Outputs, LVCMOS / LVTTL interface levels.

14, 18

Power

Voltage supply for QD0 : QD3

21, 23, 25, 27

QC0 : QC3

Output

Bank C outputs, LVCMOS / LVTTL interface levels.

22, 26

Power

Voltage supply for QC0 : QC3

29, 31, 33, 35

QB0 : QB3

Output

Bank B outputs, LVCMOS / LVTTL interface levels.

30, 34

Power

Voltage supply for QB0 : QB3

37, 39, 41, 43

QA0 : QA3

Output

Bank A outputs, LVCMOS / LVTTL interface levels.

38, 42

Power

Voltage supply for QA0 : QA3

45

CLK_SEL

Input

Pulldown Clock select input, when HIGH, selecs CLK1, nCLK1 inputs. When

LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.

46

nCLK1

Input

Pullup

inverting differential clock input

47

CLK1

input

Pulldown Non-inverting differential clock input

Function Table

Inputs

Outputs

nMR/OE

ENx

SELx

Bank X

Qx Frequency

0

X

X

Hi Z

N/A

1

1

0

Active

1

1

1

Active

1

0

X

Low

N/A