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A25L05PTM-UF Datasheet(PDF) 5 Page - AMIC Technology |
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A25L05PTM-UF Datasheet(HTML) 5 Page - AMIC Technology |
5 / 43 page A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 4 AMIC Technology Corp. Figure 1. Bus Master and Memory Devices on the SPI Bus Bus Master (ST6, ST7, ST9, ST10, Other) SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) CS3 CS2 CS1 SPI Memory Device CDO DIO S W HOLD SPI Memory Device S W HOLD SPI Memory Device S W HOLD SDI SDO SCK CDO DIO CDO DIO Note: The Write Protect ( W ) and Hold (HOLD ) signals should be driven, High or Low as appropriate. Figure 2. SPI Modes Supported MSB MSB C C DIO DO 00 1 1 CPOL CPHA |
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