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PIC18F2682 Datasheet(PDF) 59 Page - Microchip Technology |
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PIC18F2682 Datasheet(HTML) 59 Page - Microchip Technology |
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59 / 484 page  © 2007 Microchip Technology Inc. Preliminary DS39761B-page 57 PIC18F2682/2685/4682/4685 B4D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4DLC(6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B4EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B4SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4CON(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B3D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D6(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D5(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3DLC(6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B3EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3SIDL(6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B3SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B3CON(6) 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu B2D7(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D6(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D5(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D2(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. |
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