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TLC2543MEP Datasheet(PDF) 4 Page - Texas Instruments |
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TLC2543MEP Datasheet(HTML) 4 Page - Texas Instruments |
4 / 25 page www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range(2) –0.5 6.5 V VCC + VI Input voltage range (any input) –0.3 V 0.3 VCC + VO Output voltage range –0.3 V 0.3 VCC + Vref+ Positive reference voltage V 0.1 Vref– Negative reference voltage –0.1 V II Peak input current (any input) ±20 mA II Peak total input current (all inputs) ±30 mA TLC2543Q –40 125 TA Operating free-air temperature range °C TLC2543M -55 125 Tstg Storage temperature range –65 150 °C Lead temperature 1,6 mm (1/16 in) from the case for 10 s 260 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted). MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V Vref+ Positive reference voltage(1) VCC V Vref– Negative reference voltage(1) 0 V Vref+ – Vref– Differential reference voltage(1) 2.5 VCC VCC + 0.1 V Analog input voltage(1) 0 VCC V VIH High-level control input voltage VCC = 4.5 V to 5.5 V 2 V VIL Low-level control input voltage VCC = 4.5 V to 5.5 V 0.8 V Clock frequency at I/O CLOCK 0 4.1 MHz tsu(A) Setup time, address bits at DATA INPUT before I/O CLOCK ↑ (see Figure 4) 100 ns th(A) Hold time, address bits after I/O CLOCK ↑ (see Figure 4) 0 ns th(CS) Hold time, CS low after last I/O CLOCK ↓ (see Figure 5) 0 ns tsu(CS) Setup time, CS low before clocking in first address bit(2) (see Figure 5) 1.425 µs twH(I/O) Pulse duration, I/O CLOCK high 120 ns twL(I/O) Pulse duration, I/O CLOCK low 120 ns tt(I/O) Transition time, I/O CLOCK high to low(3) (see Figure 6) 1 µs tt(CS) Transition time, DATA INPUT and CS 10 µs TLC2543Q –40 125 TA Operating free-air temperature °C TLC2543M -55 125 (1) Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF– convert as all zeros (000000000000). (2) To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS ↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. (3) This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data acquisition applications where the sensor and the ADC are placed several feet away from the controlling microprocessor. 4 Submit Documentation Feedback |
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