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TLC2543MDBREP Datasheet(PDF) 10 Page - Texas Instruments |
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TLC2543MDBREP Datasheet(HTML) 10 Page - Texas Instruments |
10 / 25 page www.ti.com Access Cycle B Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Sample Cycle B A/D Conversion Interval Initialize MSB LSB Previous Conversion Data MSB LSB B7 B6 B5 B4 C7 B7 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 1 I/O CLOCK DATA OUT DATA INPUT CS EOC Initialize Hi-Z (see Note A) B3 B2 B1 B0 t(conv) Access Cycle B Sample Cycle B A/D Conversion Interval Initialize MSB LSB Previous Conversion Data MSB LSB B7 B6 B5 B4 C7 B7 A7 A6 A5 A4 A3 A2 A1 A0 Low Level 1 2 3 4 5 6 7 8 1 I/O CLOCK DATA OUT DATA INPUT CS EOC Initialize (see Note A) B3 B2 B1 B0 t(conv) Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS ↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 11. Timing for 8-Clock Transfer Using CS With MSB First A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS ↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First 10 Submit Documentation Feedback |
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