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FAIXP972MQCA4 Datasheet(PDF) 84 Page - Intel Corporation |
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FAIXP972MQCA4 Datasheet(HTML) 84 Page - Intel Corporation |
84 / 92 page Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver 84 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Table 51 lists configuration bits. Table 51. Configuration Register - Address 16, Hex 10 Bit Name Description Type 1 Default 16.15 Reserved Write as ‘0’. Ignore on Read. R/W 0 16.14 Force Link Pass 0 = Normal operation 1 = Force Link pass R/W 0 16.13 Transmit Disable 0 = Normal operation 1 = Disable Twisted Pair transmitter R/W 0 16.12 Bypass Scrambler (100BASE-TX) 0 = Normal operation 1 = Bypass Scrambler and Descrambler R/W 0 16.11 Reserved Write as ‘0’. Ignore on Read. R/W 0 16.10 Jabber (10BASE-T) 0 = Normal operation 1 = Disable Jabber Correction R/W 0 16.9 SQE (10BASE-T) 0 = Disable Heart Beat 1 = Enable Heart Beat R/W 0 16.8 TP Loopback (10BASE-T) 0 = Normal operation 1 = Disable TP loopback during half-duplex operation R/W 0 16.7 CRS Select (10BASE-T) 0 = Normal Operation 1 = CRS deassert extends to RX_DV deassert R/W 1 16.6 Reserved Write as ‘0’. Ignore on Read. R/W 0 16.5 PRE_EN Preamble Enable. 0 = Set RX_DV high coincident with SFD. 1 = Set RX_DV high and RXD = preamble when CRS is asserted. NOTE: Preamble is always enabled in 100 Mbps operation. R/W 0 16.4:3 Reserved Write as ‘0’. Ignore on Read. R/W 00 16.2 Reserved Write as ‘0’. Ignore on Read. R/W 0 16.1 Alternate NP feature 0 = Disable alternate auto negotiate next page feature. 1 = Enable alternate auto negotiate next page feature. This bit enables or disables the register bit 6.5 capability. R/W 0 16.0 Reserved Write as ‘0’. Ignore on Read. R/W 0 1. R/W = Read /Write |
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