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MC9S08QE128CLK Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc |
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MC9S08QE128CLK Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc |
27 / 52 page Electrical Characteristics MC9S08QE128 Series Advance Information Data Sheet, Rev. 3 Freescale Semiconductor 27 3.10.3 SPI Timing Table 14 and Figure 21 through Figure 24 describe the timing requirements for the SPI system. Table 14. SPI Timing No. C Function Symbol Min Max Unit —D Operating frequency Master Slave fop fBus/2048 0 fBus/2 fBus/4 Hz Hz 1D SPSCK period Master Slave tSPSCK 2 4 2048 — tcyc tcyc 2D Enable lead time Master Slave tLead 1 /2 1 — — tSPSCK tcyc 3D Enable lag time Master Slave tLag 1 /2 1 — — tSPSCK tcyc 4D Clock (SPSCK) high or low time Master Slave tWSPSCK tcyc –30 tcyc – 30 1024 tcyc — ns ns 5D Data setup time (inputs) Master Slave tSU 15 15 — — ns ns 6D Data hold time (inputs) Master Slave tHI 0 25 — — ns ns 7 D Slave access time ta —1 tcyc 8 D Slave MISO disable time tdis —1 tcyc 9D Data valid (after SPSCK edge) Master Slave tv — — 25 25 ns ns 10 D Data hold time (outputs) Master Slave tHO 0 0 — — ns ns 11 D Rise time Input Output tRI tRO — — tcyc – 25 25 ns ns 12 D Fall time Input Output tFI tFO — — tcyc – 25 25 ns ns |
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