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FALXT972MLCA4 Datasheet(PDF) 27 Page - Intel Corporation

Part # FALXT972MLCA4
Description  Single-Port 10/100 Mbps PHY Transceiver
Download  92 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

FALXT972MLCA4 Datasheet(HTML) 27 Page - Intel Corporation

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Intel
® LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
27
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.2.3.1.2
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in Figure 3 and Figure 4 (Read and Write).
MDIO Interface timing is given in Chapter 7.0, “Electrical Specifications”.
5.2.3.2
Hardware Control Interface
The LXT972M Transceiver provides a Hardware Control Interface for applications where the
MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set
device configuration. For details, see Section 5.4.4, “Hardware Configuration Settings” on
page 33.
Figure 3. Management Interface Read Frame Structure
Figure 4. Management Interface Write Frame Structure
MDC
MDIO
(Read)
32 "1"s
0110
Preamble
ST
Op Code
PHY Address
Turn
Around
Z0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
Data
Write
Read
D15
D14
D1
D0
Idle
High Z
B3489-01
MDC
MDIO
(Write)
32 "1"s
0101
Preamble
ST
Op Code
PHY Address
Turn
Around
1
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
D0
Data
Idle
Idle
Write
B3490-01


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