DJIXE972MBCA4 datasheet(41/92 Pages) INTEL

Part #	DJIXE972MBCA4

Description	Single-Port 10/100 Mbps PHY Transceiver

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Manufacturer	INTEL [Intel Corporation]

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

41

Document Number: 302875-005

Revision Date: 27-Oct-2005

5.6.7.2

Internal Digital Loopback (Test Loopback)

A test loopback function is provided for diagnostic testing of the LXT972M Transceiver. During

test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is

internally looped back by the LXT972M Transceiver and returned to the MAC.

Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by

setting the following register bits:

• Register bit 0.14 = 1 (Setting to enable loopback mode)

• Register bit 0.8 = 1 (Setting for full-duplex mode)

• Register bit 0.12 = 0. (Disable auto-negotiation.)

5.7

100 Mbps Operation

5.7.1

100BASE-X Network Operations

During 100BASE-X operation, the LXT972M Transceiver transmits and receives 5-bit symbols

across the network link.

Figure 11 shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is

not actively transmitting data, the LXT972M Transceiver sends out Idle symbols on the line.

As Figure 11 shows, the MAC starts each transmission with a preamble pattern. As soon as the

LXT972M Transceiver detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,

symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the

balance of the preamble, the SFD, packet data, and CRC.

Once the packet ends, the LXT972M Transceiver transmits the End-of-Stream Delimiter (ESD,

symbols T and R) and then returns to transmitting Idle symbols.

For details on the symbols used, see 4B/5B coding listed in Table 15, “4B/5B Coding” on page 46.

Figure 11. 100BASE-X Frame Format

P0

P1

P6

SFD

64-Bit Preamble

(8 Octets)

Start-of-Frame

Delimiter (SFD)

DA

SA

Destination and Source

Address (6 Octets each)

L1

L2

Packet Length

(2 Octets)

D0

D1

Dn

Data Field

(Pad to minimum packet size)

Frame Check Field

(4 Octets)

CRC

I0

InterFrame Gap / Idle Code

(> 12 Octets)

Replaced by

/T/R/ code-groups

End-of-Stream Delimiter (ESD)

IFG

Replaced by

/J/K/ code-groups

Start-of-Stream

Delimiter (SSD)

B3466-01

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