Electronic Components Datasheet Search |
|
DJLXT972MQCA4 Datasheet(PDF) 77 Page - Intel Corporation |
|
DJLXT972MQCA4 Datasheet(HTML) 77 Page - Intel Corporation |
77 / 92 page Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 77 Document Number: 302875-005 Revision Date: 27-Oct-2005 Table 42 lists MII status register bits. Table 42. MII Status Register #1 - Address 1, Hex 1 Bit Name Description Type 1 Default 1.15 100BASE-T4 Not Supported 0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform 100BASE-T4 RO 0 1.14 100BASE-X Full-Duplex 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform full-duplex 100BASE-X RO 1 1.13 100BASE-X Half-Duplex 0 = PHY not able to perform half-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X RO 1 1.12 10 Mbps Full-Duplex 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in full-duplex mode RO 1 1.11 10 Mbps Half-Duplex 0 = PHY not able to operate at 10 Mbps in half- duplex 1 = PHY able to operate at 10 Mbps in half-duplex mode RO 1 1.10 100BASE-T2 Full- Duplex Not Supported 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform full-duplex 100BASE-T2 RO 0 1.9 100BASE-T2 Half- Duplex Not Supported 0 = PHY not able to perform half-duplex 100BASE-T2 1 = PHY able to perform half-duplex 100BASE-T2 RO 0 1.8 Extended Status 0 = No extended status information in register 15 1 = Extended status information in register 15 RO 0 1.7 Reserved Ignore when read. RO 0 1.6 MF Preamble Suppression 0 = PHY cannot accept management frames with preamble suppressed 1 = PHY accepts management frames with preamble suppressed RO 0 1.5 Auto-Negotiation complete 0 = Auto-negotiation not complete 1 = Auto-negotiation complete RO 0 1.4 Remote Fault 0 = No remote fault condition detected 1 = Remote fault condition detected RO/LH 0 1.3 Auto-Negotiation Ability 0 = PHY is not able to perform auto-negotiation 1 = PHY is able to perform auto-negotiation RO 1 1.2 Link Status 0 = Link is down 1 = Link is up RO/LL 0 1.1 Jabber Detect 0 = Jabber condition not detected 1 = Jabber condition detected RO/LH 0 1.0 Extended Capability 0 = Basic register capabilities 1 = Extended register capabilities RO 1 1. RO = Read Only LL = Latching Low LH = Latching High |
Similar Part No. - DJLXT972MQCA4 |
|
Similar Description - DJLXT972MQCA4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |