Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MAX9242 Datasheet(PDF) 18 Page - Maxim Integrated Products

Part No. MAX9242
Description  21-Bit Deserializers with Programmable Spread Spectrum and DC Balance
Download  22 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
Logo 

MAX9242 Datasheet(HTML) 18 Page - Maxim Integrated Products

 
Zoom Inzoom in Zoom Outzoom out
 18 / 22 page
background image
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
18
______________________________________________________________________________________
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 20) is:
C = -(4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)
Fail-Safe
The MAX9242/MAX9244/MAX9246/MAX9254 have fail-
safe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the corresponding
LVDS input is open, undriven and shorted, or undriven
and parallel terminated. The fail-safe on the LVDS clock
input drives all outputs low when power is stable. Fail-
safe does not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42k
Ω (min) to provide biasing for AC-coupling (Figure 1).
To prevent switching due to noise when the clock input
is not driven, bias the clock inputs (RxCLKIN+,
RxCLKIN-) to differential +15mV by connecting a 10k
Ω
±1% pullup resistor between the noninverting input and
LVDSVCC, and a 10k
Ω ±1% pulldown resistor between
the inverting input and ground. These bias resistors,
along with the 100
Ω ±1% tolerant termination resistor,
provide +15mV of differential input. The +15mV bias
causes some small degradation of RSKM proportional to
the slew rate of the clock input. For example, if the clock
transitions 250mV in 500ps, the slew rate of 0.5mV/ps
reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC-balanced mode, the input fail-
safe circuit drives the corresponding outputs low, and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to LVDSVCC using a 10k
Ω resistor, and pull the
noninverting input down to ground using a 10k
Ω resistor.
Do not connect a termination resistor. The pullup and
pulldown resistors drive the corresponding outputs low
and prevent switching due to noise.
(7 + 2):1
7
7
100
Ω
(7 + 2):1
7
7
100
Ω
(7 + 2):1
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
7
7
100
Ω
PLL
100
Ω
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
PLL1 +
SSPLL
RO
RT
Figure 19. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn