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DJIXF972MLCA4 Datasheet(PDF) 88 Page - Intel Corporation |
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DJIXF972MLCA4 Datasheet(HTML) 88 Page - Intel Corporation |
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88 / 92 page  Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver 88 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 Table 55 lists digital configuration bits for the LXT972M Transceiver. 20.7:4 LED3 Programming bits 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status (Default) 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused R/W 0010 20.3:2 LEDFREQ5 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. R/W 00 20.1 PULSE- STRETCH 0 = Disable pulse stretching of all LEDs. 1 = Enable pulse stretching of all LEDs. R/W 1 20.0 Reserved Write as ‘0’. Ignore on Read. R/W 0 Table 54. LED Configuration Register - Address 20, Hex 14 (Sheet 2 of 2) Bit Name Description Type 1 Default 1. R/W = Read /Write. RO = Read Only. LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). Activity causes the LED to blink, regardless of the link status. 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are approximations. Not guaranteed or production tested. Table 55. Digital Configuration Register - Address 26, Hex 1A Bit Name Description Type 1 Default 26.15:12 Reserved Write as ‘0’. Ignore on Read. R/W 0000 26.11 MII Drive Strength MII Drive Strength 0 = Normal MII drive strength 1 = Increase MII drive strength R/W 0 26.10 Reserved Write as ‘0’. Ignore on Read. R/W 0 26.9 Show Symbol Error Show Symbol Error 0 = Normal MII_RXER 1 = 100BASE-X Error Signal to MII_RxER R/W 0 26.8:0 Reserved Write as ‘0’. Ignore on Read. RO 00000000 0 1. R/W = Read /Write, RO = Read Only |
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