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M36W0R6050T1 Datasheet(PDF) 1 Page - STMicroelectronics |
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M36W0R6050T1 Datasheet(HTML) 1 Page - STMicroelectronics |
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January 2007 1 1/22 1 M36W0R6050T1 M36W0R6050B1 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package Features ■ Multi-Chip Package – 1 die of 64 Mbit (4 Mb × 16) Flash memory – 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM ■ Supply voltage –VDDF = VDDP = VDDQF = 1.7 V to 1.95 V ■ Low power consumption ■ Electronic signature – Manufacturer Code: 20h – Device code (top flash configuration), M36W0R6050T1: 8810h – Device code (bottom flash configuration), M36W0R6050B1: 8811h ■ Package –ECOPACK® Flash memory ■ Programming time – 8 µs by Word typical for Fast Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options ■ Memory blocks – Multiple Bank memory array: 4 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 66 MHz – Asynchronous/ Synchronous Page Read mode – Random Access: 70 ns ■ Dual operations – Program Erase in one Bank while Read in others – No delay between Read and Write operations ■ Block locking – All blocks locked at Power-up – Any combination of blocks can be locked –WPF for Block Lock-Down ■ Security – 128-bit user programmable OTP cells – 64-bit unique device number ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block PSRAM ■ Access time: 70 ns ■ Asynchronous Page Read – Page size: 8 words – First access within page: 70 ns – Subsequent read within page: 20 ns ■ Three Power-down modes – Deep Power-Down – Partial Array Refresh of 4 Mbits – Partial Array Refresh of 8 Mbits FBGA Stacked TFBGA88 (ZA) www.st.com |
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