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M36L0R7040T0 Datasheet(PDF) 1 Page - STMicroelectronics

Part No. M36L0R7040T0
Description  128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M36L0R7040T0 Datasheet(HTML) 1 Page - STMicroelectronics

 
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December 2004
M36L0R7040T0
M36L0R7040B0
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-level, Burst) Flash Memory
1 die of 16 Mbit (1Mb x16) Pseudo SRAM
SUPPLY VOLTAGE
–VDDF = VDDP = VDDQ = 1.7 to 1.95V
–VPP = 9V for fast program (12V tolerant)
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code (Top Flash Configuration)
M36L0R7040T0: 88C4h
Device Code (Bottom Flash
Configuration) M36L0R7040B0: 88C5h
PACKAGE
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
FLASH MEMORY
SYNCHRONOUS / ASYNCHRONOUS READ
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
10µs typical Word program time using
Buffer Program
MEMORY ORGANIZATION
Multiple Bank Memory Array: 8 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
DUAL OPERATIONS
program/erase in one Bank while read in
others
No delay between read and write
operations
SECURITY
64 bit unique device number
2112 bit user programmable OTP Cells
Figure 1. Package
BLOCK LOCKING
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
–WPF for Block Lock-Down
Absolute Write Protection with VPP = VSS
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 110µA
DEEP POWER DOWN CURRENT: 10µA
TFBGA88 (ZAQ)
8 x 10mm
FBGA


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