1997 Jun 16

9

Philips Semiconductors

Preliminary specification

Audio processor for VHS hi-fi

TDA9615H

Addressing and data bytes

For programming the device (write mode) seven data byte registers are available; they are addressable via eight

subaddresses. Automatic subaddress incrementing enables the writing of successive data bytes in one transmission.

During power-on, data byte registers are reset to a default state by use of a Power On Reset (POR) circuit which signal

one data byte register is available without subaddressing.

Table 1

TDA9615H addresses and data bytes

Notes

1. Use of subaddress F0H to F7H (1111 0XXX) instead of 00H to 07H (0000 0XXX) disables the automatic subaddress

incrementing allowing continuous writing to a single data byte register.

2. The state of unused read bits are not reliable; their state may change during development.

Table 2

Status of data bytes after POR

Note

1. For eventual future compatibility it is advised to keep unused write bits equal to POR state.

DATA BYTE

ADDRESS

Write mode

Slave address byte (B8H)

10111000

Subaddress bytes (00H to 07H)

0

0 or 1

0 or 1

0 or 1

Control byte (subaddress 00)

AFM

DOC

SHH

DETH

NTSC

MUTE

STBP

STBA

Select byte (subaddress 01)

DOS1

DOS0

s5

s4

NIL3

NIL2

NIL1

NIL0

Input byte (subaddress 02)

i7

IS2

IS1

IS0

NS2

NS1

NS0

i0

Output byte (subaddress 03)

LOH

OSN

OSR

OSL

EOS

LOS

DOS

RFCM

Left volume byte

(subaddress 04)

I7

VLS

VL5

VL4

VL3

VL2

VL1

VL0

Right volume byte

(subaddress 05)

r7

VRS

VR5

VR4

VR3

VR2

VR1

VR0

Volume byte (subaddress 06)

simultaneous loading of subaddress 04 and subaddress 05 register

Power byte (subaddress 07)

CALS

VCCH

TEST

PORR

p3

p2

p1

p0

Read mode

Slave address byte (B9H)

10111001

Read byte

CALR

AUTN

POR

DATA BYTE

ADDRESS

Control byte

10001100

Select byte

0

0

0000

Input byte

Output byte

00000001

Left volume byte

1000000

Right volume byte

1000000

Power byte