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TDA9321H Datasheet(PDF) 24 Page - NXP Semiconductors |
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TDA9321H Datasheet(HTML) 24 Page - NXP Semiconductors |
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24 / 44 page  1998 Dec 16 24 Philips Semiconductors Preliminary specification I2C-bus controlled TV input processor TDA9321H Y-DELAY LINE td delay time bits YD3 to YD0 = 1011; note 6 crystal A 490 520 550 ns crystal B, C or D 530 560 590 ns td(tr) tuning range delay time with respect to 520/560 ns; 12 settings; see Table 13 −280 − +160 ns B bandwidth note 6 8 −− MHz GROUP DELAY CORRECTION (PINS GDI AND GDO); note 24 Vi(GDI)(p-p) input signal amplitude on pin GDI (peak-to-peak value) − 2.0 − V Ii(GDI) input current on pin GDI − 0.1 1.0 µA Vo(GDO)(p-p) output signal amplitude on pin GDO (peak-to-peak value) 1.8 2.0 2.2 V Vo(GDO) output top-sync level on pin GDO − 2.4 − V ∆Vo(GDO)/∆T top-sync level on pin GDO variation with temperature − 5 − mV/K Zo(GDO) output impedance on pin GDO −− 250 Ω Colour demodulation part CHROMINANCE AMPLIFIER CRACC ACC control range note 25 26 −− dB ∆V o(CRACC) change in amplitude of the output signals over CRACC −− 2dB THck(on) threshold colour killer ON colour killer from OFF to ON −40 −−35 dB hysck(off) hysteresis colour killer OFF note 6 strong signal; S/N ≥ 40 dB − 3 − dB noisy input signals − 1 − dB ACL CIRCUIT; note 26 C/CACL ACL chrominance burst ratio when the ACL starts to operate − 3.0 − REFERENCE PART Phase-locked loop; note 27 fcr catching range ±360 ±600 − Hz ∆ϕ phase shift for a ±400 Hz deviation of the oscillator frequency; note 6 −− 2 deg SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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