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MAX3984 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX3984 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 18 page PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOS asserted 0 25 μA LOS asserted; VOL 0.4V 1.0 mA LOS Open-Collector Current Sink (Note 12) 0 25 μA LOS Response Time (Note 4) Time from VIN dropping below deassert level or rising above assert level to 50% point of LOS output transition 10 μs LOS Transition Time Rise time or fall time (10% to 90%); pullup supply = 5.5V; external pullup R 4.7k 200 ns CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV Logic-High Voltage VIH 2.0 V Logic-Low Voltage VIL 0.8 V Logic-High Current IIH Current required to maintain logic-high state at VIH > +2.0V -150 μA Logic-Low Current IIL Current required to maintain logic-low state at VIL < +0.8V 350 μA 1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer _______________________________________________________________________________________ 5 Note 1: Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are limited to less than 100mV. Note 2: IN+ and IN- are single-ended, 50 Ω terminations to (VCC - 1.5V) ±0.2V. Note 3: Load is 50 Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps. Note 4: Guaranteed by design and characterization. Note 5: PE1 = PE0 = logic-high (maximum preemphasis), load is 50 Ω ±1% at each side. The pattern is 11001100 (50% edge den- sity) at 10Gbps. AC common-mode output is computed as: VACCM_RMS = RMS[(VP + VN) / 2) - VDCCM] where: VP = time-domain voltage measured at OUT+ with at least 10GHz bandwidth. VN = time-domain voltage measured at OUT- with at least 10GHz bandwidth. AC common-mode voltage (VACCM_RMS) expressed as an RMS value. DC common-mode voltage (VDCCM) = average DC voltage of (VP + VN) / 2. Note 6: Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within 2in of the output pins with Rogers 4350 dielectric, or equivalent, and ≥ 10-mil line width. For transition time, the 0% refer- ence is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state level after four consecutive logic ones. Note 7: Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mVP-P differential swing. IN_LEV = logic-low and PE0 = PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz band- width) or equivalent. See Figure 3 for setup. Note 8: Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7. Note 9: Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip (160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media induced loss and not from clock source modulation. DJ is measured at point D of Figure 2. Note 10: Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point A and the load jitter point D in Figure 3. The deterministic jitter (DJ) at the output of the transmission line must be from media induced loss and not from clock source modulation. DJ is measured at point D of Figure 3. Note 11: Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input. Note 12: True open-collector outputs. VCC = 0 and the external 4.7k Ω pullup resistor is connected to +5.5V. ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at TA = +25°C, VCC = +3.3V, unless otherwise noted.) |
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