P R E L I M I N A R Y

23

Am29240 EH Microcontroller Series

™

SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)

Preliminary

25 MHz

20 MHz

16 MHz

No.

Unit

Max

Min

Max

Min

Max

Min

Parameter Description

17

Asynchronous Input Pulse Width

LSYNC and PSYNC

Note 5

Note 5

Note 5

All others

4T

4T

4T

ns

18

UCLK Period

Note 2

30

25

20

ns

VCLK Period

Note 2

25

20

15

ns

19

UCLK High Time

Note 2

10

8

6

ns

VCLK High Time

Note 2

8

6

4

ns

20

UCLK Low Time

Note 2

10

8

6

ns

VCLK Low Time

Note 2

8

6

4

ns

21

UCLK Rise time

Note 2

0

5

0

5

0

5

ns

VCLK Rise time

Note 2

0

3

0

3

0

3

ns

22

UCLK Fall Time

Note 2

0

5

0

5

0

5

ns

VCLK Fall Time

Note 2

0

3

0

3

0

3

ns

23

Synchronous Output Valid Delay

from VCLK Rise and Fall

Note 6

1

16

1

14

1

14

ns

24

Input Setup Time to VCLK Rise

and Fall

Notes 6, 7

10

9

9

ns

25

Input Hold Time to VCLK Rise

and Fall

Notes 6, 7

0

0

0

ns

26

RAS Low Time

50

50

50

ns

27

CAS Low Time

13

13

13

ns

Notes:

For higher capacitance loads:

A. Add 1 ns output delay per 15 pF loading above 80 pF, up to 150 pF total. The minimum delay from PIAOE to PIACSx is 0 ns if

the capacitance loading on PIACSx is equal to or higher than the capacitance loading on PIAOE.

B. Add 1 ns output delay per 25 pF loading above 80 pF, up to 300 pF total. For 2/1 DRAM timing, in order to meet the setup time

RAS3–RAS0 by more than 150 pF.

C. Add 1 ns of output delay for MEMCLK to drive an external load of 100 pF.

2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.

4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,

and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of CASx for all

DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–12 on pages 25–32.)

A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.

B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.

When ID31–ID0 and IDP3–IDP0 are sampled on CASx, there is no additional setup time required for ID31–ID0 and

IDP3–IDP0 when the parity is enabled.

5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by

the CLKDIV field in the Video Control Register and VCLK.

6. Active VCLK edge depends on the CLKI bit in the Video Control Register.

7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization

delay still applies.